1. Field of the Invention
The present invention relates generally to processes for forming isolation regions in semiconductor devices, and more specifically to a process of fabricating a shallow trench isolation (STI) structure in a semiconductor device.
2. Description of the Prior Art
As semiconductor device dimensions are decreased, and device density increases, it becomes more difficult to efficiently and reliably fabricate isolation structures for separating active areas of the device. One common method of forming isolation structures for semiconductor devices is referred to as localized oxidation of silicon (LOCOS). However, the limits of the standard LOCOS process have motivated the development of new isolation processes. A trench isolation process is now widely used as it uses a fully recessed oxide, has no bird's beaks, is fully planar, and does not suffer from the field oxide thinning effect. However, the trench isolation process still suffers from problems such as "corners" effects at the trench edge that can increase device leakage current, especially when the trench is recessed.
U.S. Pat. No. 5,733,383, issued to Fazan, et al. on Mar. 31, 1998 discloses a method of using pacers used to form isolation trenches with improved corners. The trench for isolating active devices on a semiconductor substrate, is formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.
FIG. 1 shows a cross-sectional view at 10 of a typical prior art shallow trench isolation (STI) structure including isolation material 12 deposited within a trench 14 formed in a semiconductor substrate 16, the STI structure 10 having a recess, or divot, 18 formed between the isolation material 12 and the edge of the trench 14. When the isolation material 12 is etched, the recess, or divot, 18 frequently results wherein little or no isolating material 12 remains at the "corners" of the trench 14. The exposed "corners" are potential points of current leakage between regions of the active areas (not shown) of. The current leakage and other effects of the exposed corners are referred to as "corners effects". As is well understood in the art, the recess has a negative impact on I.sub.D V.sub.G characteristics of STI junctions.
Many prior art processes have been developed for manufacturing STI structures wherein the corners effect is minimized. FIGS. 2A through 2H are cross-sectional views illustrating a progression of manufacturing steps in accordance with an exemplary prior art process of manufacturing an STI structure having a smooth trench profile achieved by forming spacers around the periphery of the trench to form a dome like structure over the trench.
Referring to FIG. 2A, an insulating layer 30 is formed over a semiconductor substrate 32 in accordance with initial steps in accordance with the prior art process of manufacturing the STI structure. The insulating layer 30 is typically formed using an oxide, commonly referred to as a pad oxide. However, other suitable insulating materials are also known to be used. A nitride masking layer 34 is disposed over the insulating layer 30. Although the masking layer 34 is usually formed using a material having insulative properties (e.g., silicon nitride), conductive materials such as polysilicon and polysilicon/nitride may also be used to form the masking layer 34.
Initial steps in defining active areas 36 and trench areas 38 of the semiconductor substrate 32 include: applying a photo-resistive mask 40 over the nitride masking layer 34; etching to remove portions of the nitride masking layer 34 and insulating layer 30 in the trench area 38; etching to remove portions of the nitride masking layer 34 and insulating layer 30 in the trench area 38; etching further to remove a portion of the substrate 32; and subsequently removing the photo-resistive mask 40. Reactive ion etching (RIE) is typically used in this phase of the STI process to etch portions of layers 30 and 34, and portions of the substrate 32.
FIG. 2B shows a cross-sectional view of a trench 44 formed in the substrate 32 as a result of the step of etching an exposed portion of the substrate 32 in the trench area after the exposed portions of layers 30 and 34. The trench 44 has sidewalls which may be substantially vertical to the substrate 32, or which may be slightly sloped as shown. A first oxide layer 48 may be grown or deposited in the trench 44 via a rapid thermal oxidation (RTO) process, thereby lining the sidewalls and bottom of the trench 44 and providing greater resistance to cracking, and for passivating the trench sidewalls.
Referring to FIG. 2C, a second oxide layer 50 is deposited in the trench 44, and over the remaining portions of the insulating layer 30, and nitride masking layer 34. The second oxide layer 50 functions as an insulator, thereby providing isolation of the various electrical devices which may be fabricated on the substrate 32. The second oxide layer 50 is typically formed by a thick layer of oxide such as tetraethyl orthosilicate (TEOS), CVD-oxide, borophosphosilicate glass (BPSG), nitride, a combination thereof, or a similar insulating material. Other materials have also been found to be effective for use in isolation trenches, such as, for example, a combination of nitride and oxide, or polysilicon which has been oxidized.
FIG. 2D shows a cross-sectional view of the STI structure of FIG. 2C after planarization steps have been performed. Planarization may be accomplished by any of a variety of suitable methods, such as chemical-mechanical polishing (CMP), dry etching, or a combination thereof. As a result of the planarization steps, the top surface of the nitride masking layer 34 is exposed. The structure of FIG. 2E results after the nitride masking layer 34 is removed via a wet etching process. A portion of the second oxide layer 50 protrudes above the substrate 32 after the nitride masking layer 34 has been etched away. The protruding portion of the second oxide layer 50 has substantially vertical sides. If the insulating layer 30 were to be removed at this point using a wet etching method, a recess would be formed as shown in FIG. 1.
In order to avoid the recess and accompanying corners effects, a third oxide layer 52 may be deposited over the insulating layer 30 and second oxide layer 50 as shown in FIG. 2F. Typically, the material used to form the third oxide layer 52 has chemical properties which are substantially similar to those of the material used to form the second oxide layer 50. The third oxide layer 52 is usually deposited in accordance with a conventional chemical vapor deposition (CVP) method. The third oxide layer 52 may be formed by depositing TEOS, nitride with TEOS, or borophosphosilicate glass (BPSG). CVD-oxide may be employed. Other suitable deposited dielectrics can be used, as well as polysilicon which is subsequently oxidized. The third oxide layer 52 usually conforms to the profile of the structure, as shown in FIG. 2F. The conformal properties of the third oxide layer 52 enable the self-alignment of spacers as further described below.
A partial spacer etching step is performed, typically using dry etching, to remove all but a portion of the third oxide layer 52 thereby forming a spacer 54 surrounding the trench. Dry etching is used because it tends not to damage the active area regions which may also be disposed on the substrate. The chemical properties of the spacers 54 are substantially similar to those of the material used to form the second oxide layer 50. The spacers 54 are located on the surface of the substrate 32 at the corners of the trench, and are self-aligned to the trench.
Typically, a wet etch is then performed to remove the remaining portion of the insulating layer 30 which results in the structure of FIG. 2H. The isolating material disposed in the trench combines with the spacer 54 to form an isolation trench having a cap or dome-like covering 60 and a smooth profile. The cap 60 extends over the peripheral edges of the trench, thereby substantially overcoming the "corners" effect, and substantially reducing current leakage between the active areas 36 on the substrate.
A problem arises in the prior art STI fabrication process because it is not easy to control the dry etching process for forming the spacer 54. Referring to FIG. 2F, assuming that the third oxide layer 52 and insulating layer 30 comprise oxide, it is not easy to control the dry etching for forming the spacer 54 due to the selectivity etch ratio. Because this dry etching process is not easy to control, the insulating layer 30 is penetrated which results in damage to the active areas 36.
What is needed is an STI fabrication process which is easier to control than prior art processes.